New Contributor
New ContributorIt appears that setting the Verilog macro wasn't being saved. There is a separate button to do this in the GUI, not just the OK/Apply buttons. Once I was able to confirm it was saved, the fanout issue was resolved. Thank you - Erin
New ContributorHi ErinS,
I am having the same error as you mentioned in your post, while instantiating the LVDS SERDES IP. I could not understand what is the macro you set for this IP and what have you mentioned in the <verilog define name> (Assignments -> Settings; Verilog HDL Input; Verilog HDL macro; Name: <Verilog define name>, Setting: 1).
So can you please help me.
thank you.
