New Contributor
Regular ContributorHi,
I am not able to reproduce the error for the directive usage. Quartus 20.3 and S10 device is able to consider the macro definition correctly.
The error may be due to the `else part where tool might be routing the LVDS output to other glue logic and not the pin, because that it is the only possible way it is expecting.
Regards
New ContributorIt appears that setting the Verilog macro wasn't being saved. There is a separate button to do this in the GUI, not just the OK/Apply buttons. Once I was able to confirm it was saved, the fanout issue was resolved. Thank you - Erin
New ContributorHi ErinS,
I am having the same error as you mentioned in your post, while instantiating the LVDS SERDES IP. I could not understand what is the macro you set for this IP and what have you mentioned in the <verilog define name> (Assignments -> Settings; Verilog HDL Input; Verilog HDL macro; Name: <Verilog define name>, Setting: 1).
So can you please help me.
thank you.
