LVDS pin error on cyclone III

Question

Hi

I am making a design with the cyclone III starter kit and I want to add a LVDS transmitter interface for a display, but I get the following error:

Error: Non-differential I/O pin flash_ssram_d[0] in pin location H3 and pad 18 too close to differential I/O pin tft_out_y[0] in pin location H2 and pad 15 -- pins must be separated by a minimum of 5 pads

Do I need to separate my LVDS pins by a minimum of 5 pads from non-differential IO pins?

This sounds like quite a lot. It is almost impossible to do this if I want to keep the memory interfaces etc.

I have added an assignment for a "Fast Output Register" for my LVDS pins in the assignment editor. Is there anything else I need to do to place my LVDS pins closer to the non-differential IO pins?

Thanks

Tom

altera_forum · Answer

Hello,

the IO placement rules are documented in Cyclone III manual. They have been defined to assure signal integrity in designs with different IO standards. As a particular problem with Cyclone III, the pin assignments for parallel configuration flash are conflicting with pin requirements for DDR memory interface, so there are obviously some cases, when IO rules must be disabled to realize certain designs at all. The method has been recently discussed in the forum and is also documented in AN 466, page 16: You can assign 0 MHz toggle rate to pins to make Quartus fitter ignore them in placement rules check. If the respective pins actually are toggling, they probably may cause interferences.

Regards,

Frank

altera_forum · Answer

--- Quote Start ---

Hello,

You can assign 0 MHz toggle rate to pins to make Quartus fitter ignore them in placement rules check. If the respective pins actually are toggling, they probably may cause interferences.

Regards,

Frank

--- Quote End ---

Hi Frank,

I have a similar problem related to this but in my case the single-ended control signal that is too close to an LVDS dif pair is a very infrequent signal that seldom changes state; so I think calling it 0MHz in my case makes sense.

Anyway, my question is exactly where can I assign the toggle rate?

Thanks MAX

altera_forum · Answer

Most conveniently in the Pin Planner Tool, add a toggle rate column by the customize columns... function in Pin List and assign 0 mhz. Of course, you can also use TCL commands or the Assignment Editor.

set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to MY_SILENT_OUTPIN

altera_forum · Answer

Thanks FVM!  Got it and I learned how to add more columns in the pin planner tool thanks to you.

altera_forum · Answer

Hi,  To assign 0 MHz toggle rate to some pins can damage the internal FPGA, if this pins oscillate a lot, 5 MHz for example ???  Or, the only problem is the interference ?

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LVDS pin error on cyclone III

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