LVDS pin error on cyclone III

Hello,

the IO placement rules are documented in Cyclone III manual. They have been defined to assure signal integrity in designs with different IO standards. As a particular problem with Cyclone III, the pin assignments for parallel configuration flash are conflicting with pin requirements for DDR memory interface, so there are obviously some cases, when IO rules must be disabled to realize certain designs at all. The method has been recently discussed in the forum and is also documented in AN 466, page 16: You can assign 0 MHz toggle rate to pins to make Quartus fitter ignore them in placement rules check. If the respective pins actually are toggling, they probably may cause interferences.

Regards,

Frank