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David_MD_KIM's avatar
David_MD_KIM
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7 years ago

LVDS IO error

Hi, again

I try very simple case as attached.

But It is same error result.

Please advice how to interface lvds IO input by primitives

Thanks

3 Replies

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hello,

    Can you give me the device part number ? Did you check the clk1(n) is connected to the clk_n pin of the device ?

    Thank you ,

    Regards,

    Sree

  • David_MD_KIM's avatar
    David_MD_KIM
    Icon for New Contributor rankNew Contributor
    7 years ago

    FPGA Part number is EP4CE15F17C8N (Cyclone iV)

    However i find the reason that is naming of negative pin.

    Whenever define one of differential pin, tool generate name(n) automatically.

    After that i annotate back it to Design PIN.

    This is error happen.

    Can you teach me how to process differential PIN define correctly?

    Thanks

    David

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    There are many ways you can do ; usually way i do is assign the signal I/O standard as "LVDS " and assign the xxx_p pin in the pin planner or assignment editor or qsf assignment, then xxx_n will automatically assign by the tool .

    Hope helps ;

    Thank you,

    Regards,

    Sree