LVDS Interface and PCB layout requirments

Dear Sir,

I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter kit as shown in attached timing diagram "Working.png". But when running the same firmware on my custom board the output is always "00". I have checked continuity of traces with the meter and no open or short connections found between FPGA and LVDS connector. Attached is my schematic diagram for LVDS interface using BANK8A with VCCIO 2.5V. I have also added termination 100 ohm resistor later manually across LVDS RX lines but no success. Do I need to use external resistors for Cyclone V GX LVDS transmitter lines or are these available internally? On the Cyclone V GX starter kit these are not used. There is just direct line connections between LVDSTX+/TX- and LVDS +rx/rx-. Note that LVDS TX/RX lines are synchronized with clock.

For what reasons could the LVDs RX Inputs are always "00" on custom design board. What other additional checks do you recommend? Is there possibility of having the internal FPGA PLL or LVDS drivers faulty ? Do you have any clear guidelines of how to set up LVDS TX and LVDS RX PCB layout interface on a FR4 PCB for Cyclone V GX 5CGXFC5C6F27C6 device?

Thank you.

Regards,