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CSegu's avatar
CSegu
Icon for New Contributor rankNew Contributor
7 years ago

LVDS Interface and PCB layout requirments

Dear Sir, I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter k...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

If design is working on Dev Kit, then board need to be checked.

since we are not seeing the rx_clk, we can suspect that pll from board design point of view.

  1. Check RREF_TL, If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND.
  2. Also check VCCA_FPLL
  3. VCCH_GXBL and VCCA_FPLL must always be powered up for the PLL operation.

Try to create a simple pll design and see if we are getting expected output to eliminate the above doubt.

For LVDS PCB layout requirements refer below links

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp_lvdsboard.pdf

https://www.intel.com/content/dam/altera-www/global/en_US/others/download/board-layout-test/Altera_Device_Layout_Review_Worksheet.doc

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand