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CSegu
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7 years ago

LVDS Interface and PCB layout requirments

Dear Sir, I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter k...
CSegu's avatar
CSegu
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7 years ago
Hi Anad, Is the RREF_TL pin avaialble on pin B1 only of the ? I couldn`t find it anywhere else in 5CGXFC5C6F27C7N device. Is this requird for LVDS SERDES and REFCLK input pins also ? Thanks. Regards, Clive Seguna