Forum Discussion

CSegu's avatar
CSegu
Icon for New Contributor rankNew Contributor
7 years ago

LVDS Interface and PCB layout requirments

Dear Sir, I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter k...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Clive,

  1. Yes, B1 is the pin RREF_TL for ​Device 5CGXFC5C6F27C7N.
  2. Since we are using SERDES which uses a PLL.. we have to connect RREF_TL pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND.

Above guideline is valid If any PLL, REFCLK pin, or transceiver channel is used.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand