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CSegu
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7 years ago

LVDS Interface and PCB layout requirments

Dear Sir, I am using ALTERA LVDS_TX and LVDS_RX IPs to implement LVDS communication in loopback on a custom developed FPGA board. I have developed the firmware and runs on the CYCLONE V GX starter k...
CSegu's avatar
CSegu
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7 years ago
Dear ARS, Attached are the schematic diagrams. As shown VCCA_FPLL, VCCH_GXBL and VCCA_FPLL are all connected to power supply 2.5V. RREF_TL was not connected. To clarify is it only the RREF_TL pin that requires a 2.0-kΩ +/- 1% to GND? Is this the root cause of such problem? Do we need this resistor for LVDS SERDES also or just high speed GXB transceivers ? Do the VREFB5 of every bank require such resistor? Thank you. Regards, Clive