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Altera_Forum's avatar
Altera_Forum
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10 years ago

LVDS Differential IO pin Mapping error

HI

I have tried mapping Differential IO signals ADC_P to PIN_A29 and ADC_N to PIN_A28 using Tcl script In Quartus II 12.0 version.

In tool Its automatically creating a differential pair for ADC_P as ADC_P(n) mapped to PIN_A28 and for ADC_N creating a differential pair as ADC_N(n) mapped to PIN_A29.

So while compiling I am getting error as

Error (169290): Can't place differential I/O positive pin ADC_N at a differential I/O negative location A28

Is it enough only assigning a ADC_P signal in pin planner to PIN_A29?

I have tried removing ADC_N signal from tcl file then there is no error found.But how can i make sure ADC_P(n) signal represents ADC_N?

Please help out

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Remove 'ADC_N' from your design (as well as the tcl script), only code for the positive half of 'ADC'. Then in the pin planner assign 'ADC' to pin A29 and select the differential I/O standard you require. Quartus will automatically assign the negative half to A28.

    By adding 'ADC_N' Quartus thinks you've added another clock to your design.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    Thanks for the reply:).

    It is required to convert from Differential(ADC_P and ADC_N) to Single ended using altera premitives for further processing,removing ADC_N from the design how do i go head.

    Is it fine using ADC_P signal instead of converting to single ended?

    Does Quartus tool will take care of direct assigning of ADC_P signal?

    Please suggest.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You can do it by instantiating the primitive. However, you don't need to. Let Quartus work out for you - based on your pin assignments and I/O standard settings - that it needs the differential receiver.

    So - yes, you can code for ADC_P only.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you really want the signal names ADC_p and ADC_n instead of the tool's auto generated (n) name use this process. It is a workaround I

    use. It is a pain :-(

    1) Change all I/O standards for p and n to 2.5V

    2) Assign the single ended p and n on to the diff pin pair you want to use on the pin planner

    3) Change them one by one to LVDS_3_R standard and change their diff pair partner

    e.g. assign data_p[0] to Y6, assign data_n[0] to Y5.

    Change data_p[0] to LVDS_3_R.

    next change the complementary signal in the pin planner ‘Differential pair ‘ column from data_p[0](n) to data_n[0] and then press ‘enter’

    it will ask you if you want to change data_n[0] to LVDS_3_R. Click yes

    That’s one done, each one has to be done individually
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    HI,Nice to meet you,I have met the same question to you,have you problems been resolved?could you give me your project file,thank you very much!study by myself!email:dsg2007@126.com.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    I have mapped only P type signals in the top level file and the same in PIN MAPPING file, Tool has take care for N Type.

    And its working.

    We find difficult to map more than 20 IO signals manually both P Type ad N Type in PIN PLANNER.

    Thanks.