Altera_Forum
Honored Contributor
9 years agologging error in vhdl
I got this error several times:
my code gets successfully compiled but the error is "Logging is not supported for this item" why this error is displayed, can anyone tell !!!!!!I got this error several times:
my code gets successfully compiled but the error is "Logging is not supported for this item" why this error is displayed, can anyone tell !!!!!!What is this item? is it memory, a variable, a signal, etc.? If you could give some more information on this message such as when it occurs and in which program it will make helping you a lot easier.
I am not completely sure, but I would say Modelsim knows how to open/handle the file, but it cannot show you the changes made. As to why, I do not know.
what is the meaning of "it cannot show you the changes made"..as i haven't made any changes
Files are not synthesisable - they are only for use in simulation
Remove the file declaration and any use of it from your code.
if this file is only used in simulation, then you can put synthesis on/off pragmas around it:
<synthesisable code>
--synthesis translate_off
<stuff you dont want synthesised goes here>
--synthesis translate_on
<this area will be synthesised>