New Contributoris there system verilog syntax that can mark a signal for ILA in signal tap?
for example Xilinx Vivado has
(* mark_debug = "true" *) logic [7:0] dbg_sig; which will put it in the ILA
Super ContributorYes — in Quartus / Signal Tap, the closest SystemVerilog attribute is:
(* preserve_for_debug *) logic [7:0] dbg_sig;
This preserves the signal for debug visibility and prevents it from being optimized away during compilation.
Please note that this is not exactly the same as Vivado’s mark_debug behavior:
In Quartus, preserve_for_debug does not automatically add the signal into Signal Tap.
It preserves the signal so that it remains available and can be found more easily in the Signal Tap Node Finder.
The signal still needs to be added manually to the .stp file / Signal Tap configuration.
Also, preserve_for_debug only takes effect when Preserve for Debug is enabled in the project, for example with:
set_global_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON
So in summary, Quartus does provide an RTL syntax to mark signals for debug preservation, but it does not automatically instantiate or populate Signal Tap the way Vivado mark_debug does.
