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SanSo's avatar
SanSo
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2 years ago
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limit due to minimum port rate restriction (tmin)

Hi everyone, I am working on 10CL040YF484I7G device. And my design is to prove ping communication between two 1G ethernets with 1G speed. For this, I used 2 TSE-MAC IPs and two PLL IPs. Each PLL...
Hdl
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Could you please generate a report for the Minimum Pulse Width Violation timing and check the 'Required Width' for the Port Rate?


    The 'Required Width' for the port rate depends on the IO standard set on the pin, representing the actual specification that can be applied to that pin. It's likely that the pin can only run at 74.38 MHz. You may consider changing the IO standard to enable a faster clock.


    There are limitations I can observe based on the screenshot alone, particularly regarding timing issues. It is recommended to share your design by archiving the project (Project > Archive Project) so that I can further investigate and debug it.


    Best Regards,

    Richard Tan

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