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SanSo's avatar
SanSo
Icon for New Contributor rankNew Contributor
2 years ago
Solved

limit due to minimum port rate restriction (tmin)

Hi everyone,

I am working on 10CL040YF484I7G device. And my design is to prove ping communication between two 1G ethernets with 1G speed.


For this, I used 2 TSE-MAC IPs and two PLL IPs.

Each PLL input is 125MHz rx_clk from PHY.

And in logic, I am connecting rx fifo interface ports of MAC1 to tx fifo interface ports of MAC2 and viceversa.

Same design is working(ping happening) on DE2-115 board. Continuous ping is happening. And timing is met.

But in our custom board which is having above Cy10LP device is not working. Ping is happening but not continuous. So my doubt is timing is not meeting in this device.

Can you help me out how to solve timing issues shown in the attached images?

Thanks in advance!

Hdl
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Could you please generate a report for the Minimum Pulse Width Violation timing and check the 'Required Width' for the Port Rate?


    The 'Required Width' for the port rate depends on the IO standard set on the pin, representing the actual specification that can be applied to that pin. It's likely that the pin can only run at 74.38 MHz. You may consider changing the IO standard to enable a faster clock.


    There are limitations I can observe based on the screenshot alone, particularly regarding timing issues. It is recommended to share your design by archiving the project (Project > Archive Project) so that I can further investigate and debug it.


    Best Regards,

    Richard Tan

    p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.


3 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Could you please generate a report for the Minimum Pulse Width Violation timing and check the 'Required Width' for the Port Rate?


    The 'Required Width' for the port rate depends on the IO standard set on the pin, representing the actual specification that can be applied to that pin. It's likely that the pin can only run at 74.38 MHz. You may consider changing the IO standard to enable a faster clock.


    There are limitations I can observe based on the screenshot alone, particularly regarding timing issues. It is recommended to share your design by archiving the project (Project > Archive Project) so that I can further investigate and debug it.


    Best Regards,

    Richard Tan

    p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.


    • SanSo's avatar
      SanSo
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Richard Tan,

      Thanks for the response!

      I actually tried it yesterday from 3.3v LVCMOS to 3.3v LVTTL. Now timing is meeting and no violations.

      But somehow ping is not consistent yet. Checking what could be the cause.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Glad to hear that the timing violation has been solved.

    Since the initial issue with the timing has been solved, I will transition this thread to community support.


    At Intel, we prefer a new case for each unique technical problem, as it aids our case analysis and helps us assess our customer support requirements.

    Once you have more details on the inconsistent ping, feel free to file a separate case for your technical problem.


    Wishing you a happy holiday and a prosperous New Year in advance.


    Best Regards,

    Richard Tan