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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Latches and other warnings

Hi all,

Beginner in VHDL here. I'm trying to synthesize my VHDL code which works beautifully in the simulation, but absolutely fails to work on the real FPGA.

Being a beginner and all, I have found warnings when synthesizing, but I have no idea what exactly they mean, their implication or how to fix them. Some of them which are bugging me are:

Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches.

Warning (332060): Node: clock_divider:clock_divider1|clk_out was determined to be a clock but was found without an associated clock assignment.

Warning (332060): Node: clk3 was determined to be a clock but was found without an associated clock assignment.

I'm running at a pretty slow speed with a high duty cycle in order to try and debug the circuit, but so far I am having no luck :(

Perhaps someone here could help me out a little? I'd appreciate it.

You can find my source below (prefix links with ; thanks forum!):

https :// dl.dropbox.com/u/2167374/VHDL/alarm_clock.vhd

https :// dl.dropbox.com/u/2167374/VHDL/Clock_divider.vhd

https :// dl.dropbox.com/u/2167374/VHDL/counter_sig.vhd

https :// dl.dropbox.com/u/2167374/VHDL/counter_var.vhd

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    looking at your file names, I guess you created some latches, and generated some logic clocks too - generally things that make stuff not work on the FPGA.

    You should use a single system clock and clock enables to control when things happen.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    What do you mean by clock enables?

    I also do kind of want two clocks (besides the fact that my assignment says that I need a clock divider): a 1 Hz clock and one fast clock.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    yes, you will have a fast clock (the system clock). and then a "clock_divider" that generates clock enables, so you can follow this template: 

    
process(clk)
begin
  if rising_edge(clk) then
    if en = '1' then
      --only do something when enable is high
    end if;
  end if;
end process;

    So lets say the clock is running at 10Mhz, you only want the enable high once every 10million clock cycles.

    If you're tutor doesnt accept this approach, get a new tutor. Generated clocks are A BAD THING for internal logic.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Though I changed the code to use the clock directly and use enable signals, it isn't helping.

    At some clock speeds, it works (but there are other bugs). At some speeds, it does not work.

    And by speed, I mean the time it takes for the enable signals to be generated.

    I don't know why it happens... any ideas?

    Code is at the same place as before, including the new one

    https :// dl.dropbox.com/u/2167374/VHDL/stf.vhd