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Altera_Forum's avatar
Altera_Forum
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13 years ago

Latches and other warnings

Hi all, Beginner in VHDL here. I'm trying to synthesize my VHDL code which works beautifully in the simulation, but absolutely fails to work on the real FPGA. Being a beginner and all, I h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Though I changed the code to use the clock directly and use enable signals, it isn't helping.

At some clock speeds, it works (but there are other bugs). At some speeds, it does not work.

And by speed, I mean the time it takes for the enable signals to be generated.

I don't know why it happens... any ideas?

Code is at the same place as before, including the new one

https :// dl.dropbox.com/u/2167374/VHDL/stf.vhd