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"Intel FPGA SDK for OpenCL Best Practices Guide, Section 4.3.1" outlines how the profiler calculates the bandwidth values. These values largely depend on the frequency of the accesses (called Occupancy in the profiler which depends on how frequently the access is triggered in the loop), their size (which depends on unroll size and alignment), access contention (which depends on number of accesses/memory ports) and kernel operating frequency. Predicting/calculating these values by hand will not be very easy.
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Hum.. ok i discard the BW calculation by hand.
Do you know how LSU is connected to the memory? Is connected directly to the memory controller? because it gives me different widths for different unroll factors..
Also, it says latency LSU, is in clock cycles? What means this latency?
Thanks for always helping me bud :)
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