JESD204C example design I-series SOC Development Kit

I generated JESD204C example design project using Quartus 24.3.1 yesterday. It compiles and generated sof file. Although, the tool named the sof file as “limited”. It makes sense as it was using evaluation license.

The whole point of evaluation license was we can’t get into EEPROM one.

I was able to program one of the development board. And, I tried steps giving in user guidance nots of JESD204C for hardware test. I ran the test. However, it was unsuccessful but I was happy to further debug next day.

I came today and I first run the “Board Test GUI” for XCVR test. To make sure FMCA/B is running loopback test or not. I configure it with available FMCA sof file first and test whether FMC itself passes the loopback test or not.

It did.

Then, I went to my JESD204C example project. I opened the project and found it is asking me to recompile. I click re-compile. It threw the following error

“Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design

Quartus Prime Logic Generation tool was unsuccessful, 1 error , 0 warnings

Quartus Prime Full Compilation was unsuccessful, 3 errors , 0 warnings”

I then deleted the whole directory and start the project from scratch but end up with the same error.

I am now developing the same project in another machine. It is progressing well.

Question is ; has the Intel developed a special restriction for its evaluation IP?

Can you please clarify?