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FPGA_chap's avatar
FPGA_chap
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1 year ago

JESD204C example design I-series SOC Development Kit

I generated JESD204C example design project using Quartus 24.3.1 yesterday. It compiles and generated sof file. Although, the tool named the sof file as “limited”. It makes sense as it was using eval...
RongY_altera's avatar
RongY_altera
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1 year ago

Hi,

I'm here to help the JESD issue. Normally no special restriction for evaluating an IP. Your case is more like an environment/Quartus issue.


The error is not seen in another machine. Therefore you may try below:

1. disconnect the board and restart your server/machine

2. do not run Board Test GUI

3. create an example design and run compilation


Regards,

Rong