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FPGA_chap
New Contributor
1 year agoJESD204C example design I-series SOC Development Kit
I generated JESD204C example design project using Quartus 24.3.1 yesterday. It compiles and generated sof file. Although, the tool named the sof file as “limited”. It makes sense as it was using eval...
RongY_altera
Contributor
1 year agoIf no further questions, I'll transit this case to community support. Thanks.