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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

it's wrong!

library ieee;

use ieee.std_logic_1164.all;

entity mux1 is

port (

a,b:in std_logic_vector(7 downto 0);

sel:in std_logic_vector(1 downto 0);

c :out std_logic_vector (7 downto 0)

);

end mux1;

architecture example of mux1 is

begin

process(a,b,s)

begin

if (sel="00")then

c<="00000000"

elsif (sel="01")then

c<=a;

elsif (sel="10")then

c<=b;

else

c<=(others=>'Z');

end if;

end process;

end example ;

Error (10500): VHDL syntax error at mux1.vhd(16) near text "elsif"; expecting ";"

can you give a advice .thank you very much!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    In VHDL, every instruction has to terminated with ";", as the error message says. Usually, the error location is before the reported line number, in this case one line above. Shouldn't be too hard to find...