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Altera_Forum's avatar
Altera_Forum
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16 years ago

it's wrong!

library ieee; use ieee.std_logic_1164.all; entity mux1 is port ( a,b:in std_logic_vector(7 downto 0); sel:in std_logic_vector(1 downto 0); c :out std_logic_vector (7 downto 0) )...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

In VHDL, every instruction has to terminated with ";", as the error message says. Usually, the error location is before the reported line number, in this case one line above. Shouldn't be too hard to find...