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AccelerComm's avatar
AccelerComm
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4 years ago

Is there a way to speed up Intel FPGA Gate level simulations?

Hi,

I was wondering if anyone has identified a method of decreasing the time it takes for an FPGA Gate level simulation for an Intel part? This can be on Xcelium or Questa/Modelsim. Another FPGA competitor takes x50 faster. Any help much appreciated.

Kind Regards

7 Replies

  • AccelerComm's avatar
    AccelerComm
    Icon for New Contributor rankNew Contributor
    4 years ago

    Thank you for your help.
    We couldn't get the simulator (Questa) to accept those arguements.
    ​
    The best way we found was to change the `timescale 1 ns / 1 ps you can only change it to 1/1, 1/10 or 1/100, but essentially the Frequency of our design means we don't have to evaluate events at picoseconds, we could evaluate at 100s of picoseconds - this helped in some cases, but in other cases it was hard to tell.
  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Sorry can you clarify- are you trying to speed up the simulation process or have the simulation show a bigger/smaller timescale?


    Nurina


  • AccelerComm's avatar
    AccelerComm
    Icon for New Contributor rankNew Contributor
    4 years ago

    We are trying to speed up the simulation time and wondered if changing the timescale may increase the simulation time for the FPGA gatelevel netlist.

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thank you for the clarification. Yes, generally adjusting the timescale can speed up simulation, but this is not the only factor for simulation speed.


    It's possible that some IP's are causing the long simulation time. It's sometimes expected and sometimes not. You can take a look at our KDB to see if it shouldn't happen to any IP you're using, often there are workarounds: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/kdb-filter.html


    RTL simulation is always faster than gate-level simulation, so do that. It's also much easier to debug. For IP, be sure to use simulation models. Quartus Prime Pro third party simulation user guide your reference: https://www.intel.com/content/www/us/en/programmable/documentation/gft1513990268888.html#mwh1409960618998


    You can also use profiler on QuestaSim to identify what's taking so much time. Only use what you need. Otherwise the simulator will have to do too much work and take too much time.


    This Quora thread has a similar discussion: https://www.quora.com/How-do-I-reduce-simulation-time-while-simulating-in-a-Verilog-simulator


    Regards,

    Nurina


  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

    Regards,
    Nurina

    P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!