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AccelerComm's avatar
AccelerComm
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5 years ago

Is there a way to speed up Intel FPGA Gate level simulations?

Hi, I was wondering if anyone has identified a method of decreasing the time it takes for an FPGA Gate level simulation for an Intel part? This can be on Xcelium or Questa/Modelsim. Another FPGA co...
AccelerComm's avatar
AccelerComm
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5 years ago

Thank you for your help.
We couldn't get the simulator (Questa) to accept those arguements.
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The best way we found was to change the `timescale 1 ns / 1 ps you can only change it to 1/1, 1/10 or 1/100, but essentially the Frequency of our design means we don't have to evaluate events at picoseconds, we could evaluate at 100s of picoseconds - this helped in some cases, but in other cases it was hard to tell.