Is there a way to speed up Intel FPGA Gate level simulations?

Thank you for your help.

We couldn't get the simulator (Questa) to accept those arguements.

The best way we found was to change the `timescale 1 ns / 1 ps you can only change it to 1/1, 1/10 or 1/100, but essentially the Frequency of our design means we don't have to evaluate events at picoseconds, we could evaluate at 100s of picoseconds - this helped in some cases, but in other cases it was hard to tell.