Is there a way to speed up Intel FPGA Gate level simulations?

Hi,

Thank you for the clarification. Yes, generally adjusting the timescale can speed up simulation, but this is not the only factor for simulation speed.

It's possible that some IP's are causing the long simulation time. It's sometimes expected and sometimes not. You can take a look at our KDB to see if it shouldn't happen to any IP you're using, often there are workarounds: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/kdb-filter.html

RTL simulation is always faster than gate-level simulation, so do that. It's also much easier to debug. For IP, be sure to use simulation models. Quartus Prime Pro third party simulation user guide your reference: https://www.intel.com/content/www/us/en/programmable/documentation/gft1513990268888.html#mwh1409960618998

You can also use profiler on QuestaSim to identify what's taking so much time. Only use what you need. Otherwise the simulator will have to do too much work and take too much time.

This Quora thread has a similar discussion: https://www.quora.com/How-do-I-reduce-simulation-time-while-simulating-in-a-Verilog-simulator

Regards,

Nurina