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AccelerComm's avatar
AccelerComm
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4 years ago

Is there a way to speed up Intel FPGA Gate level simulations?

Hi, I was wondering if anyone has identified a method of decreasing the time it takes for an FPGA Gate level simulation for an Intel part? This can be on Xcelium or Questa/Modelsim. Another FPGA co...
AccelerComm's avatar
AccelerComm
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4 years ago

We are trying to speed up the simulation time and wondered if changing the timescale may increase the simulation time for the FPGA gatelevel netlist.