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ARach7's avatar
ARach7
Icon for New Contributor rankNew Contributor
6 years ago

Is there a plan to fix VHDL code of Cyclonev_atom? it contain plenty of errors.

Cyclonev VHDL flavor gives elaboration error with VCS. They are justified.

Is there an ETA for a fix ?​

%sed -n '6482,6599p;6599q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > t.vhd

%cat t.v

module tb();

cyclonev_termination cyclonev_termination ();

endmodule

%vlogan +v2k /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v t.v

%vhdlan t.vhd

%vcs tb

Error-[BADFORMALSPEC] Bad formal part specified

Formal port 'SCANIN' in component 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

(t_2.vhd:26) cannot be found in module

'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

(/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

rules of association lists.

Error-[BADFORMALSPEC] Bad formal part specified

Formal port 'SCANOUT' in component 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

(t_2.vhd:26) cannot be found in module

'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

(/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

rules of association lists.

Error-[BADFORMALSPEC] Bad formal part specified

Formal generic 'A_OCT_TEST_3' in component 'CYCLONEV_TERMINATION_ENCRYPTED'

(t.vhd:46) cannot be found in module 'CYCLONEV_TERMINATION_ENCRYPTED'

(/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

rules of association lists.

Error-[ANALERR_SIZEMISMATCH1] Size mismatch

Mismatch found between the actual named 'OTHERENSER', whose type size is 9,

and the formal named 'OTHERENSER', whose type size is 10. Actual

'OTHERENSER' is defined in COMPONENT named CYCLONEV_TERMINATION_ENCRYPTED in

file t.vhd at line 71. Formal 'OTHERENSER' is defined in MODULE named

CYCLONEV_TERMINATION_ENCRYPTED in file

/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v

at line 25.

12 Replies

  • ARach7's avatar
    ARach7
    Icon for New Contributor rankNew Contributor

    I am afraid that the last reply not answer the problem.

    You have VHDL file with Verilog instances, that mismatch in various aspects (ports, etc).

    It is not a matter of flow , it is a pure design bug.

    I think I am wasting my time with this kind of support.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    I actually tried to compile all the simulation library files without stripping it. The error mentioned did not occur. I was thinking if we miss out some of the important files that cause this error. This is the reason why I suggest to compile/simulate using the proper flow above and see if the same error occurs. Then we can check one by one to figure out what is the root cause of this.

    Thanks for understanding.

    Thanks.

    (1507332018)