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ARach7's avatar
ARach7
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6 years ago

Is there a plan to fix VHDL code of Cyclonev_atom? it contain plenty of errors.

Cyclonev VHDL flavor gives elaboration error with VCS. They are justified. Is there an ETA for a fix ?​ %sed -n '6482,6599p;6599q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclon...
ARach7's avatar
ARach7
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6 years ago

I am afraid that the last reply not answer the problem.

You have VHDL file with Verilog instances, that mismatch in various aspects (ports, etc).

It is not a matter of flow , it is a pure design bug.

I think I am wasting my time with this kind of support.