Is it possible to force all I/O HighZ before programming (CPLD Max_V)

On our circuit board, the TDO line as been linked through another I/O pin which is not used in the project (BGA 100 package). The ​first programmation was good. However the unused I/O are linked to ground (why is it the default configuration in Quartus assignment?). It is no more possible to programm the device again, as the TDO is now connected to GND. It seems possible to place all I/O in HighZ mode using the JTAG chain debugger and instruction 0x0B. But this is not kept for further instruction. Do you have an idea or I place the board in rubish box ? Or is it possible to send program file without TDO checking ? Thank you in advance.