Contributor
Super ContributorCan you create a snippet of code with the design that able to compile? Attached the design.qar here so that I can look into it and get back to you. A simple design will do since it only involve ifelse statement.
Contributorcode now is compiled removing elsif, old file still is on HDD, this is an Ethernet 10Base T module, now it is working, as I wrote.
Where can you host my code? This run on proprietary board with RJ45 magnetics and protection, normally is not used on Ethernet but proprietary biphase manchester at higher speed, this is not shareable.
This module got addressed to have a direct fast debug tools due to reduced pin count on device and consquently trouble to use internal/external Logic Analyzer.
The two code snippet on top are the trouble, it generate packet identifier, it is an UDP but is treated as ICMP reply.
Constants are for sure set to 1 not 5, development board has a lot of free pin where I connected the LA probe, Saleae has limit on decoding Manchester when more than 3 input get used but I used Agilent too and I confirm the trouble.
Code where it fail is a rudimental state machine driven by a counter, counter work, using original Verilog module it work, using new pathced module work.
Please give me some time to review old errant module to be compiled on and I send. I have to leave office now, I return back in two hour then I try post code and some images of board, one board is closed, the other can be freely shared with schematics too.
How large can be attached file? I am not ready now to publish back on Open IP Core.
Regards.
Roberto
