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Altera_Forum's avatar
Altera_Forum
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16 years ago

IP Core Internal Nodes Synthesized Away

Hi,

I have a problem regarding some IP core nodes were synthesized away by Quartus II. Therefore, i couldn't add them to the waveform editor. Also, i couldn't write a timing constraint using Assignment Editor, as they will be ignored.

I know how to use the command such as /*synthesis keep*/ or /*synthesis preserve*/ or /*synthesis noprune*/. However in this case, Altera IP is encrypted and i have no way to view nor edit the source file.

Sometimes, in order to view all the internal nodes, i have to switch to Modelsim. But, in this case, i need to write timing constraint from one node to another node, which i have to use Assignment Editor by Quartus II.

Kindly advise me on how to prevent all nodes of the IP core from being synthesized away or how can i come about in writing the timing constraint.

Thank you :)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I guess I'm wondering why you're trying to make timing constraint assignments to them if they are being synthesized away.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hmm...

    For example, how could i write a timing constraint from a D-FF1 output to another D-FF2 input? So that Quartus II can place that 2 FF not too far from each other...

    The input of the D-FF2 usually would be synthesized away by Quartus, can anyone explain this?

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Why do you think to need constraining internal nodes? The design compiler should perfectly know about the internal timing requirements from you specification of external timing. And it will surely minimize routing delays, if necessary.

    Regarding "synthesizing away", it's all in your HDL code, I think. Quartus is synthesizing a functional equivalent of your hardware description. It's following what you said rather than what you possibly mean. If an essential circuit function can't be clearly specified by the HDL description, you may need special synthesis attributes or settings. But you didn't yet clarify, why it should be necessary with your design.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm using timing constraint for bundle data. I would like to make sure that my data from (RegA -> RegB) is faster than my request signal so that RegB samples the correct data. Can you tell me the exact steps to do it, as i'm kinda beginner in digital design, esp in establishing timing constraint...

    Thanks