Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

IP Core Internal Nodes Synthesized Away

Hi, I have a problem regarding some IP core nodes were synthesized away by Quartus II. Therefore, i couldn't add them to the waveform editor. Also, i couldn't write a timing constraint using ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm using timing constraint for bundle data. I would like to make sure that my data from (RegA -> RegB) is faster than my request signal so that RegB samples the correct data. Can you tell me the exact steps to do it, as i'm kinda beginner in digital design, esp in establishing timing constraint...

Thanks