IP Core Internal Nodes Synthesized Away

Why do you think to need constraining internal nodes? The design compiler should perfectly know about the internal timing requirements from you specification of external timing. And it will surely minimize routing delays, if necessary.

Regarding "synthesizing away", it's all in your HDL code, I think. Quartus is synthesizing a functional equivalent of your hardware description. It's following what you said rather than what you possibly mean. If an essential circuit function can't be clearly specified by the HDL description, you may need special synthesis attributes or settings. But you didn't yet clarify, why it should be necessary with your design.