Forum Discussion

LucasMendes's avatar
LucasMendes
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Intradomain Skew Problem

I am synthesizing my Verilog design into a Ciclone V (5CSXFC6D6F31C6) and trying to increase FMAX. The design is a SOC (top level) with a processor, a dual port data memory (IPcore), a dual port ROM ...
Compilation
Timing
  • sstrell's avatar
    sstrell
    1 year ago

    You need a complete .sdc file that defines all clock domains in the design as well as input and output delay constraints in order to fully constrain the design.

    Your timing report shows a very long data path delay between the memory and the CPU. Is this a CPU of your own design? The data is going through many levels of logic to reach its destination. If you built this CPU, you may want to add pipelining to the design to break up these long combinational logic paths.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

As the initial question has been resolved, I will transitioning this thread to community support.


If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.


Thank you and have a great day!


Best Regards,

Richard Tan