Forum Discussion
New ContributorIntradomain Skew Problem
You need a complete .sdc file that defines all clock domains in the design as well as input and output delay constraints in order to fully constrain the design.
Your timing report shows a very long data path delay between the memory and the CPU. Is this a CPU of your own design? The data is going through many levels of logic to reach its destination. If you built this CPU, you may want to add pipelining to the design to break up these long combinational logic paths.
Super ContributorThank you Sstrell for answering.
Additionally, you can checkout the application note on how to create sdc constraint for input/output interface constraints:
You may look for timing related training in our FPGA Training webpage:
https://learning.intel.com/developer/pages/128/intelr-fpga-training
e.g.
Understanding Timing Analysis in FPGAs
Best Design Practice for Timing Closure
Constraining Source Synchronous Interface
Quartus Prime Pro Software Timing Analysis - Part 1 to 5
We also have user guide:
https://www.intel.com/content/www/us/en/docs/programmable/683588/17-1/quick-start-tutorial.html
https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/using-the-timing-analyzer.html
Regards,
Richard Tan
