Forum Discussion
New ContributorIntradomain Skew Problem
You need a complete .sdc file that defines all clock domains in the design as well as input and output delay constraints in order to fully constrain the design.
Your timing report shows a very long data path delay between the memory and the CPU. Is this a CPU of your own design? The data is going through many levels of logic to reach its destination. If you built this CPU, you may want to add pipelining to the design to break up these long combinational logic paths.
Super ContributorAre you failing timing somewhere (provide the timing report) or are you just trying to "push the envelope" and get to a certain Fmax? What does your .sdc file look like?
New ContributorI am trying to understand where is the critical path of my design to improve it. I believe (I could be wrong) that this issue is most related to the configuration of the tool (Quartus), than the way I created the logic (like the suggestions about long combinational path).
The timing report I attached is from the top failing path (torv32 is the processor, and "dmem" is the dual port RAM memory IP core). If that's not what you are asking, please correct me.
It was my first time using Timing Analyzer, so I used a .sdc file created by Quartus, and it only has these lines:
set_time_format -unit ns -decimal_places 3
create_clock -name {CLK} -period 1.000 -waveform { 0.000 0.500 } [get_ports {CLK}]
set_clock_uncertainty -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -hold 0.060
- sstrell
You need a complete .sdc file that defines all clock domains in the design as well as input and output delay constraints in order to fully constrain the design.
Your timing report shows a very long data path delay between the memory and the CPU. Is this a CPU of your own design? The data is going through many levels of logic to reach its destination. If you built this CPU, you may want to add pipelining to the design to break up these long combinational logic paths.
- LucasMendes
Thank you for your support. I will try to create a more complete .sdc file. Do you know of any references on how to create this type of file?
The CPU is my own design and is already pipelined. I may need to break these long combinational paths, but a more complete timing analysis (with a complete .sdc file) will certainly help me identify the best place to break.
