Internal Error Quartus 24.1 Line 731

I'm getting ready to release an FFT core for Agilex 7. I've been compiling with Quartus 23.2 to get resources estimates, which has been working fine. However, I recently tried a compile with Quartus 24.1 and I get an internal error.

The error is this:

Internal Error: Sub-system: QHD, File: /quartus/comp/qhd/qhd_design.cpp, Line: 731
!is_partition(iname)
Stack Trace:
  Quartus         0x13f4db: QHD_DESIGN_IMPL::create_partition_impl(HDB_INSTANCE_NAME*, QDB_VLNV const&, bool) + 0xc9 (comp_qhd)
  Quartus         0x13fff6: QHD_DESIGN_IMPL::create_partition(HDB_INSTANCE_NAME*, QDB_VLNV const&) + 0xe (comp_qhd)
  Quartus         0x137a4b: QHD_DESIGN_IMPL::create_top_partition() + 0x81 (comp_qhd)
  Quartus         0x142fbb: QHD_DESIGN_IMPL::load_flat_block(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, bool) + 0x98d (comp_qhd)
  Quartus          0x56d86: FLNG::FLNG_TASK_MANAGER::load_previous_digest(char const*, QTL_HASH<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, QTL_OPS<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, void> >&) + 0x6a0 (da_flng)
  Quartus          0x89961: FLNG::FLNG_TASK_MANAGER::has_task_assignments_changed(FLNG::FLNG_FLOW*, std::deque<FLNG::FLNG_TASK*, std::allocator<FLNG::FLNG_TASK*> > const&, FLNG::FLNG_TASK*, ACF_SMART_ACTION_DIGEST&) + 0x9cf (da_flng)
  Quartus          0x8b3cd: FLNG::FLNG_TASK_MANAGER::get_tasks_invalidated_by_change(FLNG::FLNG_FLOW*, bool, bool) + 0x919 (da_flng)
  Quartus          0x93334: FLNG::FLNG_TASK_MANAGER::invalidate_tasks_impacted_by_assignment_changes(FLNG::FLNG_FLOW*, bool) + 0x74 (da_flng)
  Quartus          0x93a5f: FLNG::FLNG_TASK_MANAGER::bind_flow(FLNG::FLNG_FLOW*, QString const&, QString const&, bool, bool, bool, bool, bool) + 0x3e1 (da_flng)
  Quartus          0x94263: FLNG::FLNG_TASK_MANAGER::bind_flow(FLNG::FLNG_OBJECT_ID const&, QString const&, QString const&, bool, bool, bool, bool, bool) + 0x8f (da_flng)
  Quartus          0xe5932: FLNG::FLNG_SERVICE::bind_flow(FLNG::FLNG_OBJECT_ID const&, QString const&, QString const&, bool) + 0x4a (da_flng)
  Quartus          0xe78c9: flng_dyn_run_flow + 0xa0b (da_flng)
  Quartus          0x5aa58: flow_run_flow_engine(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > > const&, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > > const&) + 0xbe (sys_flow)
  Quartus          0x62c12: flow_execute_flow + 0x1230 (sys_flow)
  Quartus          0x4753b: TclInvokeStringCommand + 0x7b (tcl8.6)
  Quartus          0x4bb47: TclNRRunCallbacks + 0x67 (tcl8.6)
  Quartus          0x4cf29: TclEvalEx + 0x599 (tcl8.6)
  Quartus          0xf40fe: Tcl_FSEvalFileEx + 0x21e (tcl8.6)
  Quartus          0xf4246: Tcl_EvalFile + 0x26 (tcl8.6)
  Quartus          0x2708e: qexe_evaluate_tcl_script(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x388 (comp_qexe)
  Quartus          0x29dec: qexe_do_tcl(QEXE_FRAMEWORK*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > > const&, bool, bool) + 0x71b (comp_qexe)
  Quartus          0x2f962: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x5a5 (comp_qexe)
  Quartus         0x4041ae: qsh_main(int, char const**) + 0x5c (quartus_sh)
  Quartus          0x43f80: msg_main_thread(void*) + 0x10 (ccl_msg)
  Quartus          0x44a00: msg_thread_wrapper(void* (*)(void*), void*) + 0x8c (ccl_msg)
  Quartus          0x1fcfd: mem_thread_wrapper(void* (*)(void*), void*) + 0x9d (ccl_mem)
  Quartus           0xe168: err_thread_wrapper(void* (*)(void*), void*) + 0x1e (ccl_err)
  Quartus          0x44929: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xd3 (ccl_msg)
  Quartus         0x4041f0: main + 0x26 (quartus_sh)
  System           0x29d90: (c)
  System           0x29e40: __libc_start_main + 0x80 (c)
  Quartus         0x403d09: _start + 0x29 (quartus_sh)

End-trace

The TCL to compile is rather simple:

project_open synthesize_forward
load_package flow
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
  set pin_name [get_name_info -info full_path $name_id]
  if { $pin_name == "clk" } {
     post_message "No VIRTUAL_PIN assignment to $pin_name"
  } else {
     post_message "Making VIRTUAL_PIN assignment to $pin_name"
     set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
  }
}
export_assignments
execute_flow -compile

The qsf file doesn't have anything I would consider suspicious:

#set_global_assignment -name FAMILY ""
set_global_assignment -name DEVICE AGIC040R39A2I3VC
set_global_assignment -name TOP_LEVEL_ENTITY BxBFFT_12_6_complex_BxBIF
set_global_assignment -name SDC_FILE synthesize_forward.sdc
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY reports

set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
#set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation

set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name VERILOG_FILE BxBFFT_source_verilog/BxBFFT_12_6_complex.sv
set_global_assignment -name VERILOG_MACRO "FORWARD=1"
set_global_assignment -name VERILOG_MACRO "FULL_FORWARD_FLOW_CONTROL=0"
set_global_assignment -name VERILOG_MACRO "INPUT_ORDER=0"
set_global_assignment -name VERILOG_MACRO "OUTPUT_ORDER=2"

set_global_assignment -name VERILOG_MACRO "REAL_WIDTH=18"
set_global_assignment -name VERILOG_MACRO "GAIN_CONTROL_STRATEGY=10"

set_global_assignment -name VERILOG_MACRO "__SYNTHESIS__"
set_global_assignment -name VERILOG_MACRO "SYNTHESIS"
set_global_assignment -name VERILOG_MACRO "ALTERA_SYNTHESIS"

The sdc file is quite basic:

set_time_format -unit ns -decimal_places 3
create_clock -name clk -period 1.429 [get_ports clk]

The qpf file is one line:

PROJECT_REVISION = "synthesize_forward.qsf"

I don't believe this has any relation to the System Verilog code itself, since I get the same error no matter what code I try to compile. I compile with

quartus_sh -t synthesize_forward.tcl

Any help is greatly appreciated.