Internal Error Quartus 24.1 Line 731

To hopefully facilitate finding a solution or workaround, I've created a simple test case (attached). This design has only a single register, but fails to compile under Quartus 24.1. It successfully compiles under Quartus 23.2. I'm not trying to compile a full design here; I'm just trying to verify that Quartus understands the verilog, compiles it into a working netlist, and that I can get resource estimates. Hence virtual pins. All files are included, as well as all Quartus outputs for both 23.2 and 24.1. The README.TXT file says more.

If anyone can see how to achieve these goals that works in both versions of Quartus, I'd appreciate it. Also, why do I have to change the DEVICE name between Quartus 23.2 and 24.1? Isn't it physically the same chip?