Occasional ContributorInstantiation of the module in a toplevel module
Hi,
I was trying to understand the file structure and code dependencies in my Quartus Prime pro project "fifo". I have created a design in Platform Designer System with just an Avalon FIFO IP and was trying to simulate the output.
I have a couple of questions. My working directory FIFO_TEST.zip is attached with this message.
1. I assume the module fifo_qsys_fifo_0 thatinstantiated in the top-level module \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v is from \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\sim\fifo_qsys_fifo_0.v, right? I would like to know how the \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v scans through folders to find fifo_qsys_fifo_0.v .
2. I was going through the code \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\altera_avalon_fifo_181\sim\fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq.v, which I assume have an instantiation in the \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\sim\fifo_qsys_fifo_0.v . I saw a module fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq_single_clock_fifo, which has an instance of a module "scfifo" with a name "single_clock_fifo". Basically I did not find any code in my working directory carrying a module "scfifo". May I know where this module is called from?
3. In my project, I selected the avalon streaming input to avalon mm read output port configuration. I am bit confused with the assignments in the fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq_map_avalonst_to_avalonmm module of \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\altera_avalon_fifo_181\sim\fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq.v .
"assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];"
Is there any specific reason why the bits [31 : 24] in the Avalon streaming input data is assigned to the [7 : 0] bits of Avalon memory map output?.
4. I also would like to know what is the significance of the input parameter "fifo_0_out_address" in the avalon mm data transfer (please see \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v). I am bit confused that since its a slave read port, and why we needed an address as input to FIFO?
I am curious that it has the name "address", but its just one bit wide. I would like to know how its value (setting 0 or 1) in testbench can affect the output data flow?
Thank you.
Hi,
When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:
As this time channel had been being assigned some value.
Check document details:
If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.
Thanks,
Best regards,
Sheng
