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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Instantiation of the module in a toplevel module

Hi, I was trying to understand the file structure and code dependencies in my Quartus Prime pro project "fifo". I have created a design in Platform Designer System with just an Avalon FIFO IP and wa...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:

    As this time channel had been being assigned some value.

    Check document details:

    If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.

    Thanks,

    Best regards,

    Sheng

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thank you very much!

I have noticed that setting the "fifo_0_out_address"=0 in the simulation test bench (\FIFO_TEST\fifo_qsys\sim\fifo_qsys_tb.v) an output data that is having opposite endianness to that of "fifo_0_out_address"=1 . I have a hard time in understanding why this happening. Do you have any thought regarding this?

The screenshot showing the simulation output for setting (simulated using the fifo_qsys_tb.v attached)

#1fifo_0_out_address=0

#10fifo_0_out_address=1

#10fifo_0_out_address=0

#10fifo_0_out_address=1

is attached Capture_modelsim1.PNG (please see the readdata and fifo_0_out_address signals in the modelsim wave output). I am confused why endian conversion in FIFO core is affected by the avalon mm input signal fifo_0_out_address ?