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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Instantiation of the module in a toplevel module

Hi, I was trying to understand the file structure and code dependencies in my Quartus Prime pro project "fifo". I have created a design in Platform Designer System with just an Avalon FIFO IP and wa...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:

    As this time channel had been being assigned some value.

    Check document details:

    If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.

    Thanks,

    Best regards,

    Sheng

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:

As this time channel had been being assigned some value.

Check document details:

If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.

Thanks,

Best regards,

Sheng