Forum Discussion
Occasional ContributorInstantiation of the module in a toplevel module
Hi,
When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:
As this time channel had been being assigned some value.
Check document details:
If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.
Thanks,
Best regards,
Sheng
Super ContributorSince you're talking about simulation, this is all about your simulation tool, not Quartus.
1) In Quartus, the connection is made by adding either the generated .qip file or the .qsys file itself to your Quartus project. In a simulation tool, you would point to the working directory where all the files are located. Platform Designer generates scripts for simulation tools to allow them to simulate a system, but it depends on your simulation tool.
2) scfifo would be the generic IP module name. It probably references back to the Quartus and Platform Designer installation.
3) Avalon streaming and Avalon memory-mapped have opposite endianness (I forget which is big and which is little). This must be doing the required bit (byte) swizzling.
4) (slave=agent) This is an agent interface that is accessed by a host in the system to read the data output and (optionally) status registers from the FIFO. As such, a host would need to set the address to read in the FIFO (either the FIFO data output or a particular status register, like the FIFO full indicator for example). If it's only one bit wide, then you probably aren't using the status interface (user guide says it's 3 bits wide when enabled). It might leave the single bit input there for compatibility with the rest of the system
More info:
https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/st-sink-to-mm-read-agent.html
https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/status-interface.html
Occasional ContributorThank you very much for helping me. sorry I forgot to mention that my simulation tool is ModelSim. Regarding the point 3, is there any specific reason why we need bit swizzling here?. Is it something needed for the memory-mapped data transfer? If I manually modify
"assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];"
to have the same endianness, or it's not recommended?
I am curious that if I am streaming a bitstream data (say "100000100010001") to FIFO and then do a Memory Map read though the output port to a peripheral (say DDR4), then how this endianness mis-match will be corrected (I mean how the correct bit sequence "100000100010001" will be saved in the DDR4)
Regarding the point 4, Yeh I am not using the status interface. I am just curious that if my host is some other IP, then the FIFO address will be set automatically by the "Assign Base-address"? or we have to do something manually?
I have noticed that setting the "fifo_0_out_address"=0 in the simulation test bench (\FIFO_TEST\fifo_qsys\sim\fifo_qsys_tb.v) an output data that is having opposite endianness to that of "fifo_0_out_address"=1 . I have a hard time in understanding why this happening. Do you have any thought regarding this?
Thank you very much.
- sstrellNo do not edit any files generated by PD. The whole point of the tool is for you to build your system how you want it and then let PD build the interconnect for you. There is no need for you to go in and look at or make changes to the generated code.
Read the user guide I linked to which is also linked to in PD. That explains how to use IP like the FIFO.
