Instantiating VHDL entity in Systemverilog

I am out of town for a week, so I can’t try compiling the code for a few days. I can post the original VHDL code I am trying to rewrite in Systemverilog. So what I am trying to find out is what is the comparable Systemverilog for the following VHDL.

entity DE10_Nano_FB_DB25 is

port (

--------- GPIO ---------

GPIO_0 : inout std_logic_vector(35 downto 0);

GPIO_1 : inout std_logic_vector(35 downto 0) );

end DE10_Nano_FB_DB25;

architecture arch of DE10_Nano_FB_DB25 is

HostMot2_inst : entity work.HostMot2_cfg

port map (

-- GPIO_0 -- DB25-P2

iobits( 0) => GPIO_0(16), -- PIN 1

iobits( 1) => GPIO_0(17), -- PIN 14

iobits( 2) => GPIO_0(14), -- PIN 2

— ...

iobits(34) => GPIO_1(16), -- PIN 1

iobits(35) => GPIO_1(17), -- PIN 14

iobits(36) => GPIO_1(14) -- PIN 2

);

end arch;

When I comment out this code the rest of it compiles without errors (but useless).

Thanks in advance.

I have pasted in a section of code followed by the errors it generates. I edited in the line# 0402 to show where the errors start. I have attached the complete file in case the segment is insufficient.

HostMot2_cfg HostMot2_inst(

.ibus(hm_datai), // input [buswidth-1:0] ibus_sig

.obus(hm_datao), // output [buswidth-1:0] obus_sig

.addr(hm_address), // input [addrwidth-1:2] addr_sig -- addr => A(AddrWidth-1 downto 2),

.readstb(hm_read), // input readstb_sig

.writestb(hm_write), // input writestb_sig

.clklow(fpga_clk_50), // input clklow_sig -- PCI clock --> all

.clkmed(hm_clk_med), // input clkmed_sig -- Processor clock --> sserialwa, twiddle

.clkhigh(hm_clk_high), // input clkhigh_sig -- High speed clock --> most

.irq(irq), // output irq -- int => LINT, ---> PCI ?

.dreq(/* open */), // output dreq_sig

.demandmode(/* open */), // output demandmode_sig

.iobits( {

// GPIO_0 -- DB25-P2

0402 GPIO_0(17), // PIN 14

GPIO_0(14), // PIN 2

GPIO_0(15), // PIN 15

GPIO_0(12), // PIN 3

GPIO_0(13), // PIN 16

GPIO_0(10), // PIN 4

GPIO_0(11), // PIN 17

GPIO_0(08), // PIN 5

GPIO_0(09), // PIN 6

GPIO_0(06), // PIN 7

GPIO_0(07), // PIN 8

GPIO_0(04), // PIN 9

GPIO_0(05), // PIN 10

GPIO_0(02), // PIN 11

GPIO_0(03), // PIN 12

GPIO_0(00), // PIN 13

// GPIO_0 -- DB25-P3

GPIO_0(34), // PIN 1

GPIO_0(35), // PIN 14

GPIO_0(32), // PIN 2

GPIO_0(33), // PIN 15

...

} ),

// .leds[0](GPIO_0[01]), // output [ledcount-1:0] leds_sig -- leds => LEDS

// .leds[1](GPIO_0[19]),

// .leds[2](GPIO_1[01]),

// .leds[3](GPIO_1[19]),

.leds( { GPIO_0(01), // output [ledcount-1:0] leds_sig -- leds => LEDS

GPIO_0(19),

GPIO_1(01),

GPIO_1(19) } ),

.liobits(/* open */), // inout [lIOWidth-1:0] -- lhm2_iobits

.rates(/* open */) // output [4:0] rates_sig

);

endmodule

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(402): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 402

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(403): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 403

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(404): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 404

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(405): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 405

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(406): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 406

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(407): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 407

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(408): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 408

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(409): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 409

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(410): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 410

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(411): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 411

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(412): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 412

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(413): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 413

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(414): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 414

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(415): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 415

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(416): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 416

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(417): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 417

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(419): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 419

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(420): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 420

Error (10153): Verilog HDL Function Call or Function Declaration error at DE10_Nano_FB_DB25.sv(421): identifier "GPIO_0" is not a function File: /home/acondit/ArmProcs/mksocfpga/HW/QuartusProjects/DE10_Nano_FB_DB25/DE10_Nano_FB_DB25.sv Line: 421

--- Quote Start ---

Unlike VHDL, SV doesn't allow bit-selects in module instance port names. You can use the port name with a concatenation as port expression.

.iobits({GPIO_0(16),GPIO_0(17), ... })

--- Quote End ---

I changed

.iobits({GPIO_0(16),GPIO_0(17), ... }) to .iobits({GPIO_0[16],GPIO_0[17], ... }) and it gets rid of those errors.

So thanks for at least pointing me in the right direction.