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Honored Contributor
Honored ContributorInstantiating VHDL entity in Systemverilog
I am trying to instantiate a VHDL entity in systemverilog. In the VHDL entity “iobits” is defined as follows. iobits : inout std_logic_vector (67 downto 0); because I am interfacing to...
Altera_ForumHonored Contributor
Honored ContributorUnlike VHDL, SV doesn't allow bit-selects in module instance port names. You can use the port name with a concatenation as port expression.
.iobits({GPIO_0(16),GPIO_0(17), ... })
