Instantiating VHDL entity in Systemverilog

I am out of town for a week, so I can’t try compiling the code for a few days. I can post the original VHDL code I am trying to rewrite in Systemverilog. So what I am trying to find out is what is the comparable Systemverilog for the following VHDL.

entity DE10_Nano_FB_DB25 is

port (

--------- GPIO ---------

GPIO_0 : inout std_logic_vector(35 downto 0);

GPIO_1 : inout std_logic_vector(35 downto 0) );

end DE10_Nano_FB_DB25;

architecture arch of DE10_Nano_FB_DB25 is

HostMot2_inst : entity work.HostMot2_cfg

port map (

-- GPIO_0 -- DB25-P2

iobits( 0) => GPIO_0(16), -- PIN 1

iobits( 1) => GPIO_0(17), -- PIN 14

iobits( 2) => GPIO_0(14), -- PIN 2

— ...

iobits(34) => GPIO_1(16), -- PIN 1

iobits(35) => GPIO_1(17), -- PIN 14

iobits(36) => GPIO_1(14) -- PIN 2

);

end arch;

When I comment out this code the rest of it compiles without errors (but useless).

Thanks in advance.