Altera_Forum
Honored Contributor
Honored ContributorInstantiating VHDL entities into a Verilog top level
I would like to instantiate some VHDL entities into A Verilog top level.
Any ides on how to do this?Forum Discussion
2 Replies
Altera_ForumYou don't have to do anything special. Just map the ports in your Verilog instantiation as usual.
- Altera_Forum
Thanks, that did it.
