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Altera_Forum
Honored Contributor
Honored ContributorInstantiating VHDL entities into a Verilog top level
I would like to instantiate some VHDL entities into A Verilog top level. Any ides on how to do this?
Altera_ForumHonored Contributor
Honored ContributorYou don't have to do anything special. Just map the ports in your Verilog instantiation as usual.
