Honored ContributorCould anybody tell me how to instantiate primitive DFF with an an inverted clock input in Quartus-II as attached inst11? When I right click the DFF in the schematic/block editor of Quartus-II, its Properties - Symbol Properties - Ports - Inversion radio buttons are all greyed out. Many thanks.
Honored ContributorYou can place an inverter, Quartus is supposed to know how to handle an inverted clock. It also does in HDL implementation.
Honored ContributorThanks, FvM.
If I can't instantiate the DFF with an inverted clock, I have to do this way or implement it using the dff mega-core. However, doing that way will introduce extra clock delay or clock skew as mentioned many times in Altera's documnetations or other documentations. The attached diagram is extracted from "Timing Analysis of Internally Generated Clocks in Timequest" by kwalt in the Altera Forum. I don't know how he managed this with Quartus-II. Cheers.Honored ContributorIf doing a schematic, I either:
-throw down a FF with an inverter before the clock - take the clock and drive it through an inverter and name the net, then just use that net to drive the FF clock(this is cleaner if a lot of signals are getting the inversion, where the first one is better if it's only a small number, as it clearly shows the inversion) Note that both methods have the inverter get absorbed into the LAB clock inversion and there is no clock skew and no timing issues. Now, the schematic you attached will have a skew issue to the second FF, since your clock goes through an AND gate(and because your clock is cascaded from another FF). So I would avoid that.Honored ContributorDo you mean that the inverted clock net can be shared by many objects while it can still be synthesized into the LAB clock inversion?
Anyway, the attached schematic is also recommanded by Altera or use the alkclkctrl megacore function for dedicated clock ouput paths. Any better idea?Honored ContributorThe architecture is generally a global clock tree that fans out to every register in the device, and within each lab that clock tree can be inverted. THis is all handled by synthesis, i.e. if you only do one inversion of the net, synthesis will pass that down to the LAB level. If you do a bunch of inversions on each register, synthesis will figure out if they can be joined or not. Clock inversions are taken care of for you physically and you only have to deal with them logically.
As for the circuit, I don't like it since it will skew your clock. I would either use the altclkctrl block and drive the enable of it, or infer a clock enable in all the downstream logic. Either one will work.Honored ContributorIf you consider, that some Altera IP is using inverted clocks up to the speed limits of the device, e.g. software DDIO input in Cyclone family, you should basically trust Quartus synthesis in this regard. You can additonally constrain the respective register timing, if you have special requirements.
Regarding the discussed gated clock circuit, the Altera suggestion is about the way to design a gated clock glitch free, which is the least but necessary requirement for a clock. If it can also provide suitable timing depends on timing of the data input. In case of an unrelated asynchronous signal, the register input timing won't become worse by processing it with a ripple clock. So the circuit actually can serve a purpose. If data is originated from the system clock domain, it shouldn't be used.Honored ContributorGuys, thank you very much indeed for your explanations.
