Instantiate primitive DFF with an an inverted clock input

If you consider, that some Altera IP is using inverted clocks up to the speed limits of the device, e.g. software DDIO input in Cyclone family, you should basically trust Quartus synthesis in this regard. You can additonally constrain the respective register timing, if you have special requirements.

Regarding the discussed gated clock circuit, the Altera suggestion is about the way to design a gated clock glitch free, which is the least but necessary requirement for a clock. If it can also provide suitable timing depends on timing of the data input. In case of an unrelated asynchronous signal, the register input timing won't become worse by processing it with a ripple clock. So the circuit actually can serve a purpose. If data is originated from the system clock domain, it shouldn't be used.